//#ifdef __USE_CMSIS
#include "LPC17xx.h"
//#endif

//#include <cr_section_macros.h>

// Variable to store CRP value in. Will be placed automatically
// by the linker when "Enable Code Read Protect" selected.
// See crp.h header for more information
//#include <NXP/crp.h>
//__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "uartinfo.h"
#include "sysinfo.h"
#include "PINCON.h"

#define LED 0xffffffff //(1L << 22)
#define DELAY 2000000

int SCSReg(void);
int RSIDReg(void); // a finir
int EXTINTReg(void);
int EXTMODEReg(void);
int EXTPOLARReg(void);
int PLL0CONReg(void);
int PLL0CFGReg(void);
int PLL0STATReg(void);
int PLL0FEEDReg(void);

int CCLKCFGReg(void);

int PCONPReg(void);

void PLL0Setup(void);

// UART2
void UART2_Init(int baudrate);
char *infoTxt;
char *tampon;
#define CMD_SIZE 32
char *cmd;

// Si programmation MCU bloquee:
// http://support.code-red-tech.com/CodeRedWiki/DebugAccessChip

int RS232Main(void)
{
    volatile static int i = 0, count = 0 ;
   	char c;
	  int index=0;
	
    infoTxt =(char*)malloc(2048); // Alloue sur le Tas
    tampon = (char*)malloc(256);
    cmd = (char*)malloc(CMD_SIZE);

	//SystemInit();  // A documenter
	//UART2PinsEnable(); // P0.15=TXD1, P0.16=RXD1

/*
	SCSReg();
	PCONPReg();
	EXTINTReg();
	EXTMODEReg();
	EXTPOLARReg();
	PLL0CONReg();
	PLL0CFGReg();
	PLL0STATReg();
	PLL0FEEDReg();
	CCLKCFGReg();
*/

	//printf("\nSystemCoreClock = %d Hz\n", SystemCoreClock);
	//printf("Clock Source (0=Internal RC, 1=Main Osc, 2=RTC) = %d\n",LPC_SC->CLKSRCSEL);

	UART2PinsEnable(); // P0.15=TXD1, P0.16=RXD1
	UART2_Init(9600*1); // Setup UART2 to 9600 baud

	sprintf(tampon,"\nTIGER SystemCoreClock = %d Hz\nTIGER Clock Source (0=Internal RC, 1=Main Osc, 2=RTC) = %d\n\n", SystemCoreClock,LPC_SC->CLKSRCSEL);
	strcpy(infoTxt,tampon);
	 UART2_PrintString(infoTxt);

	SCSReg();
	 UART2_PrintString(infoTxt);
	PCONPReg();    // Prob with uVision ?
	 UART2_PrintString(infoTxt);	 
	CCLKCFGReg();
	 UART2_PrintString(infoTxt);
	PLL0STATReg();
	 UART2_PrintString(infoTxt);
	PLL0CFGReg();
	 UART2_PrintString(infoTxt);	 
	PLL0CONReg();
	 UART2_PrintString(infoTxt);	 
	EXTPOLARReg();
	 UART2_PrintString(infoTxt);

	//printf("Attente Commande (terminee par LF)...\n");
	strcpy(infoTxt,"Attente Commande (terminee par LF)...\n");
	 UART2_PrintString(infoTxt);


	while(1)
	{
		// Pas necessaire, enable loopback suffit
		//LPC_UART2->IER |= bit0|bit1|bit2|bit3;  // enables INTs
		//LPC_UART2->MCR |= bit4; // enable loopback
		//UART2_Sendchar(lb);

		c = UART2_Getchar();	// ! GetChar bloquant temps que rien de recu
		// acculume les caracteres
		cmd[index++] = c;
		cmd[index] = '\0';
		if ( index >= CMD_SIZE ) index=0;

		if (c == '\n' )
		{
		  cmd[index-1] = '\0'; // enleve le LF
		  index=0; // RAZ commande
    	  sprintf(tampon,"CMD=[%s]\n",cmd);
    	   UART2_PrintString(tampon);
          if ( strcmp(cmd,"clock")==0 )
          {
        	  strcpy(infoTxt,"\n-> clock\n");
        	   UART2_PrintString(infoTxt);

    		 	SCSReg();
     			 UART2_PrintString(infoTxt);
         		CCLKCFGReg();
         		 UART2_PrintString(infoTxt);
                PLL0CONReg();
        		 UART2_PrintString(infoTxt);
        		PLL0CFGReg();
        		 UART2_PrintString(infoTxt);
        		PLL0STATReg();
       		     UART2_PrintString(infoTxt);

        	  	  sprintf(tampon,"\nSystemCoreClock = %d Hz\nClock Source (0=Internal RC, 1=Main Osc, 2=RTC) = %d\n\n", SystemCoreClock,LPC_SC->CLKSRCSEL);
        		  strcpy(infoTxt,tampon);
        		   UART2_PrintString(infoTxt);
          }
          else if ( strcmp(cmd,"change")==0 )
          {
        	  strcpy(infoTxt,"-> change l'horloge\n");
        	   UART2_PrintString(infoTxt);

        	    //PLL0Setup();

        		//UART2_Init(9600*1); // Setup UART2 to 9600 baud

         	  strcpy(infoTxt,"Toujours Vivant !!!\n");
         	   UART2_PrintString(infoTxt);
          }
          else if ( strcmp(cmd,"cmd2")==0 )
          {
        	  strcpy(infoTxt,"-> CMD2\n");
        	   UART2_PrintString(infoTxt);
          }
          else if ( strcmp(cmd,"cmd3")==0 )
          {
        	  strcpy(infoTxt,"-> CMD3\n");
        	   UART2_PrintString(infoTxt);
          }
              else
              {
            	  strcpy(infoTxt,"-> ?\n");
            	   UART2_PrintString(infoTxt);
              }
		}
	}


    // PINSEL Pin Selection Function (PINSEL0 -> PINSEL9)
    // 00 = Primary Function, typically GPIO (reset default)
    // 01 = First Alternate Function.
    // 01 = Second Alternate Function.
    // 01 = Third Alternate Function.

    // LPC_PINCON Pin Connect Block dans LPC17xx.h
    LPC_PINCON->PINSEL0 &= (!0x00003000); // b11000000000000 si !
    //printf("PINSEL0 = %d\n", (!0x00003000));

     // p.122
     // IO Port Direction Control Register -> direction of each Pin
     // 1 for OUTPUT, 0 for INPUT
     LPC_GPIO0->FIODIR = 0xffffffff;

     // (Fast)MASK Register for Port. Writes, Sets, Clears and Reads to Port
     // via FIOPIN, FIOSET and FIOCLR
     // ALTER or RETURN ONLY THE BITS ENABLED BY ZEROS IN THIS REGISTER
  	 LPC_GPIO0->FIOMASK = 0x00000000;  // si 0xffffffff, aucune pin n'est modifiee par SET ou CLR


    while (1)
    {
        // (Fast)PORT PIN Value Register, Current State of Digital Port Pins is read from this
    	// Register Regardless of Pin Direction or alternate function (except ADC input)
    	// !! The Value Read is MASKED and ANDing with INVERTED FIOMASK.
    	// Writing to this register places corresponding values in all bits enabled by Zeros in FIOMASK
    	//LPC_GPIO0->FIOPIN;

       // (Fast)CLEAR Register using FIOMASK -> writing 1s produces LOW at corresponding Pin
       // 1. ! Only Bits enabled by 0 in FIOMASK can be altered !
       // 2. ! WRITING 0s HAS NO EFFECT !
       LPC_GPIO0->FIOCLR = LED;
       //printf("#%d OFF\n", count); // ! semihosting project
        	for (i = 0; i < DELAY; i++) ;

       // (Fast)SET Register using FIOMASK -> writing 1s produces HIGH at corresponding Pin
       // 1. ! Only Bits enabled by 0 in FIOMASK can be altered !
       // 2. Reading this Register return the current Contents of the Port Output Register
       // 3. ! WRITING 0s HAS NO EFFECT !
        LPC_GPIO0->FIOSET = LED;
        //printf("#%d ON\n", count);  // ! semihosting project
        	for (i = 0; i < DELAY; i++) ;
      count++;
    }
    //while(1) ;
//   return(0);
}

int SCSReg(void)
{
	strcpy(infoTxt,"\n*** SCS System Controls Register 0x400FC1A0 ***\n");
	if ( LPC_SC->SCS & bit4 ) strcat(infoTxt," --- b4 Set   - Main Oscillator Range is [15-25] MHz\n");
	else strcat(infoTxt," --- b4 Clear - Main Oscillator Range is [1-20] MHz\n");
	if ( LPC_SC->SCS & bit5 ) strcat(infoTxt," --- b5 Set   - Main Oscillator is Enable (needs Quartz on XTAL1&2)\n");
	else strcat(infoTxt," --- b5 Clear - Main Oscillator Range is Disabled\n");
	if ( LPC_SC->SCS & bit6 ) strcat(infoTxt," --- b6 Set   - Main Oscillator Ready to be used as Clock Source (can be enabled by b5)\n");
	else strcat(infoTxt," --- b6 Clear - Main Oscillator Range is Not Ready to be used as a Clock Source\n");
 return 0;
}
int RSIDReg(void)
{
	strcpy(infoTxt,"\n*** RSID Reset Source Identification Register 0x400FC180 ***\n");
	strcat(infoTxt,"b0=POR, b1=EXTR, b2=WDTR, b3=BODR\n");
    // TODO
  return 0;
}
int EXTINTReg(void)
{
	// Tip : Apres chaque changement de mode il faut faire un clear du bit concerne
	strcpy(infoTxt,"\n*** EXTINT External Interrrupt Flag Register 0x400FC140 ***\n");
	if ( LPC_SC->EXTINT & bit0 ) strcat(infoTxt," --- b0 Set - EINT0 set\n");
	else strcat(infoTxt," --- b0 Clear - EINT0 cleared\n");
	if ( LPC_SC->EXTINT & bit1 ) strcat(infoTxt," --- b1 Set - EINT1 set\n");
	else strcat(infoTxt," --- b1 Clear - EINT1 cleared\n");
	if ( LPC_SC->EXTINT & bit2 ) strcat(infoTxt," --- b2 Set - EINT2 set\n");
	else strcat(infoTxt," --- b2 Clear - EINT2 cleared\n");
	if ( LPC_SC->EXTINT & bit3 ) strcat(infoTxt," --- b3 Set - EINT3 set\n");
	else strcat(infoTxt," --- b2 Clear - EINT3 cleared\n");
 return 0;
}
int EXTMODEReg(void)
{
	// Reg. Bits select whether each EINT pin is Level or Edge-Sensitive
	// A manipuler avec l'Int. concernee disabled !
	strcpy(infoTxt,"\n*** EXTMODE External Interrrupt Mode Register 0x400FC148 ***\n");
	if ( LPC_SC->EXTMODE & bit0 ) strcat(infoTxt," --- b0 Set - EINT0bar is Edge-Sensitive\n");
	else strcat(infoTxt," --- b0 Clear - EINT0bar is Level-Sensitive\n");
	if ( LPC_SC->EXTMODE & bit1 ) strcat(infoTxt," --- b1 Set - EINT1bar is Edge-Sensitive\n");
	else strcat(infoTxt," --- b1 Clear - EINT1bar is Level-Sensitive\n");
	if ( LPC_SC->EXTMODE & bit2 ) strcat(infoTxt," --- b2 Set - EINT2bar is Edge-Sensitive\n");
	else strcat(infoTxt," --- b2 Clear - EINT2bar is Level-Sensitive\n");
	if ( LPC_SC->EXTMODE & bit3 ) strcat(infoTxt," --- b3 Set - EINT3bar is Edge-Sensitive\n");
	else strcat(infoTxt," --- b3 Clear - EINT3bar is Level-Sensitive\n");
 return 0;
}
int EXTPOLARReg(void)
{
	strcpy(infoTxt,"\n*** EXTMODE External Interrrupt Mode Register 0x400FC14C ***\n");
	if ( LPC_SC->EXTPOLAR & bit0 ) strcat(infoTxt," --- b0 Set - EINT0bar is High-Active or Rising-Edge Sensitive (depending on EXTMOD0)\n");
	else strcat(infoTxt," --- b0 Clear - EINT0bar is Low-Active or Falling-Edge Sensitive (depending on EXTMOD0)\n");
	if ( LPC_SC->EXTPOLAR & bit1 ) strcat(infoTxt," --- b1 Set - EINT1bar is High-Active or Rising-Edge Sensitive (depending on EXTMOD1)\n");
	else strcat(infoTxt," --- b1 Clear - EINT1bar is Low-Active or Falling-Edge Sensitive (depending on EXTMOD1)\n");
	if ( LPC_SC->EXTPOLAR & bit2 ) strcat(infoTxt," --- b2 Set - EINT2bar is High-Active or Rising-Edge Sensitive (depending on EXTMOD2)\n");
	else strcat(infoTxt," --- b2 Clear - EINT2bar is Low-Active or Falling-Edge Sensitive (depending on EXTMOD2)\n");
	if ( LPC_SC->EXTPOLAR & bit3 ) strcat(infoTxt," --- b3 Set - EINT3bar is High-Active or Rising-Edge Sensitive (depending on EXTMOD3)\n");
	else strcat(infoTxt," --- b3 Clear - EINT3bar is Low-Active or Falling-Edge Sensitive (depending on EXTMOD3)\n");
 return 0;
}
int PLL0CONReg(void)
{
	strcpy(infoTxt,"\n*** PLL0CON PLL0 Control Register 0x400FC080 ***\n");
	if ( LPC_SC->PLL0CON & bit0 ) strcat(infoTxt," --- b0 Set   - PLL0 Enable (after valid PLL0 feed, activates PLL0 and allow it to Lock the requested Freq.)\n");
	else strcat(infoTxt," --- b0 Clear - PLL0 Disable\n");
	if ( LPC_SC->PLL0CON & bit1 ) strcat(infoTxt," --- b1 Set   - PLL0 Connected (after valid sequence) PLL0 is the Source Clock for CPU & AHB peripherals\n");
	else strcat(infoTxt," --- b1 Clear - PLL0 Not Connected, PLL0 is NOT the Source Clock for CPU\n");
 return 0;
}
int PLL0CFGReg(void) // Contains PLL0 Multiplier and Divider
{
	int msel0 = (LPC_SC->PLL0CFG &  0x7fff) + 1; // M (! M-1 is stored)
	int nsel0 = ((LPC_SC->PLL0CFG & 0xff0000)>>16) + 1; // N (! N-1 is stored)
	int predivider; // N
	float Fcco;	
  // ! changements effectifs apres une "PLL feed sequence" correct
	strcpy(infoTxt,"\n*** PLL0CFG PLL0 Configuration Register 0x400FC084 ***\n");
	// Bits 0:14 = Multiplier
	// Bits 16:26 = Predivider

	if ( (msel0 >= 6) && (msel0 <= 512) )
	{
		sprintf(tampon, " --- Found a Valid Multiplier between 6 and 512. Multiplier(M) = %d, Pre-divider(N) = %d\n", msel0, nsel0);
		strcat(infoTxt, tampon);		
	}
	else
	{	
	 switch ( msel0 )  // ! La valeur stockee dans PLL0CFG est M-1
	 {   // Multiplier values for PLL0 with a 32 kHz input
		case 4272 :		predivider=1;	Fcco=279.9698; break;
		case 4395 :		predivider=1;	Fcco=288.0307; break;
		case 4578 : 	predivider=1;	Fcco=300.0238; break;
		case 4725 : 	predivider=1;	Fcco=309.6576; break;
		case 4807 :		predivider=1;	Fcco=315.0316; break;
		case 5127 :		predivider=1;	Fcco=336.0031; break;
		case 5188 :		predivider=1;	Fcco=340.0008; break;
		case 5400 :		predivider=1;	Fcco=353.8944; break;
		case 5493 :		predivider=1;	Fcco=359.9892; break;
		case 5859 :		predivider=1;	Fcco=383.9754; break;
		case 6042 :		predivider=1;	Fcco=395.9685; break;
		case 6075 :		predivider=1;	Fcco=398.1312; break;
		case 6104 :		predivider=1;	Fcco=400.0317; break;
		case 6409 :		predivider=1;	Fcco=420.0202; break;
		case 6592 :		predivider=1;	Fcco=432.0133; break;
		case 6750 :		predivider=1;	Fcco=442.3680; break;
		case 6836 :		predivider=1;	Fcco=448.0041; break;
		case 6866 :		predivider=1;	Fcco=449.9702; break;
		case 6958 :		predivider=1;	Fcco=455.9995; break;
		case 7050 :		predivider=1;	Fcco=462.0288; break;
		case 7324 :		predivider=1;	Fcco=479.9857; break;
		case 7425 :		predivider=1;	Fcco=486.6048; break;
		case 7690 :		predivider=1;	Fcco=503.9718; break;
		case 7813 :		predivider=1;	Fcco=512.0328; break;
		case 7935 :		predivider=1;	Fcco=520.0282; break;
		case 8057 :		predivider=1;	Fcco=528.0236; break;
		case 8100 :		predivider=1;	Fcco=530.8416; break;
		case 8545 :		predivider=2;	Fcco=280.0026; break;
		case 8789 :		predivider=2;	Fcco=287.9980; break;
		case 9155 :		predivider=2;	Fcco=299.9910; break;
		case 9613 :		predivider=2;	Fcco=314.9988; break;
		case 10254 :	predivider=2;	Fcco=336.0031; break;
		case 10376 :	predivider=2;	Fcco=340.0008; break;
		case 10986 :	predivider=2;	Fcco=359.9892; break;
		case 11719 :	predivider=2;	Fcco=384.0082; break;
		case 12085 :	predivider=2;	Fcco=396.0013; break;
		case 12207 :	predivider=2;	Fcco=399.9990; break;
		case 12817 :	predivider=2;	Fcco=419.9875; break;
		//case 12817 :	predivider=3;	Fcco=279.9916; break;
		case 13184 :	predivider=2;	Fcco=432.0133; break;
		//case 13184 :	predivider=3;	Fcco=288.0089; break;
		case 13672 :	predivider=2;	Fcco=448.0041; break;
		case 13733 :	predivider=2;	Fcco=450.0029; break;
		//case 13733 :	predivider=3;	Fcco=300.0020; break;
		case 13916 :	predivider=2;	Fcco=455.9995; break;
		case 14099 :	predivider=2;	Fcco=461.9960; break;
		case 14420 :	predivider=3;	Fcco=315.0097; break;
		case 14648 :	predivider=2;	Fcco=479.9857; break;
		case 15381 :	predivider=2;	Fcco=504.0046; break;
		//case 15381 :	predivider=3;	Fcco=336.0031; break;
		case 15564 :	predivider=3;	Fcco=340.0008; break;
		case 15625 :	predivider=2;	Fcco=512.0000; break;
		case 15869 :	predivider=2;	Fcco=519.9954; break;
		case 16113 :	predivider=2;	Fcco=527.9908; break;
		case 16479 :	predivider=3;	Fcco=359.9892; break;
		case 17578 :	predivider=3;	Fcco=383.9973; break;
		case 18127 :	predivider=3;	Fcco=395.9904; break;
		case 18311 :	predivider=3;	Fcco=400.0099; break;
		case 19226 :	predivider=3;	Fcco=419.9984; break;
		case 19775 :	predivider=3;	Fcco=431.9915; break;
		case 20508 :	predivider=3;	Fcco=448.0041; break;
		case 20599 :	predivider=3;	Fcco=449.9920; break;
		case 20874 :	predivider=3;	Fcco=455.9995; break;
		case 21149 :	predivider=3;	Fcco=462.0070; break;
		case 21973 :	predivider=3;	Fcco=480.0075; break;
		case 23071 :	predivider=3;	Fcco=503.9937; break;
		case 23438 :	predivider=3;	Fcco=512.0109; break;
		case 23804 :	predivider=3;	Fcco=520.0063; break;
		case 24170 :	predivider=3;	Fcco=528.0017; break;
		default : sprintf(tampon," --- ! %d IS AN UNKNOWN MULTIPLIER, this should not happens !\n", msel0);
		          strcat(infoTxt, tampon);
							break;
	 }
  }
	sprintf(tampon," --- PLL0CFG Multiplier=%d, Pre-divider=%d\n", msel0, nsel0);
	strcat(infoTxt, tampon);
 return 0;
}
int PLL0STATReg(void) // CRO, provides actual PLL0 parameters in effect
{  // ! PLL0STAT may disagree with values found in PLL0CON and PLL0CFG because changes
   // to those registers do not take effect until a proper PLL0 feed has occurred.
	int msel0 = (LPC_SC->PLL0STAT & 0x7fff); // M (! M-1 is stored)
	int nsel0 = ((LPC_SC->PLL0STAT & 0xff0000)>>16); // N (! N-1 is stored)	
	int plle0 = LPC_SC->PLL0STAT & bit24;
	int pllc0 = LPC_SC->PLL0STAT & bit25;
	
	strcpy(infoTxt,"\n*** PLL0STAT PLL0 Status Register 0x400FC088 ***\n");
	// Bits 0:14 = Multiplier bit15 reserved
	msel0 = msel0 + 1;
	// Bits 16:26 = Predivider
	nsel0 = nsel0 + 1;
	sprintf(tampon," --- PLL0STAT Multiplier=%d, Pre-divider=%d\n", msel0, nsel0);
	strcat(infoTxt, tampon);
	
	if ( plle0  ) strcat(infoTxt," --- b24 Set - (PLLE0) PLL0 Enabled\n");
	else strcat(infoTxt," --- b24 Clear - (PLLE0) PLL0 turned Off (e.g. Power Down Mode)\n");
	if ( pllc0 ) strcat(infoTxt," --- b25 Set - (PLLC0)\n");
	else strcat(infoTxt," --- b25 Clear - (PLLC0)\n");
	if ( LPC_SC->PLL0STAT & bit26 ) strcat(infoTxt," --- b26 Set - (PLOCK0) PLL0 is Locked on the requested Freq.\n");
	else strcat(infoTxt," --- b26 Clear - PLL0 Not Locked\n");
	if ( pllc0 && plle0 ) // 1 - 1
		strcat(infoTxt," --- -> PLL0 is Active and has been connected as the System Clock Source\n");
	if ( !pllc0 && plle0) // 0 - 1
		strcat(infoTxt," --- -> PLL0 is Active but NOT YET Connected, PLL0 can be connected after PLOCK0 (bit26) is asserted\n");
	if ( pllc0 &&  !plle0 ) // 1 - 0, idem 0 - 0
		strcat(infoTxt," --- -> PLL0 is Turned OFF and Disconnected (PLL0 has not been Enable)\n");
	if ( !pllc0 && !plle0 )
		strcat(infoTxt," --- -> PLL0 is Turned OFF and Disconnected\n");
 return 0;
}
int PLL0FEEDReg(void) //
{  //
  strcpy(infoTxt,"\n*** PLL0FEED PLL0 Feed Register 0x400FC08C ***\n");
	sprintf(tampon," --- PLL0FEED = %d\n", LPC_SC->PLL0FEED);
	strcat(infoTxt, tampon);
 return 0;
}
int CCLKCFGReg(void)
{
  // CCLKCFG reg. controls the division of the PLL0 output before it is used by the
  // CPU. When PLL0 is bypassed, the division may be by 1. When PLL0 is running, the
  // output must be divided in order to bring the CPU clock frequency (CCLK) within operating
  // limits. An 8-bit divider allows a range of options, including slowing CPU operation to a low
  // rate for temporary power savings without turning off PLL0
	int clock = LPC_SC->CCLKCFG & 0xff; //0b11111111;
  strcpy(infoTxt,"\n*** CCLKCFG CPU Clock Configuration register 0x400FC104 ***\n");
	sprintf(tampon," --- CCLKCFG = % d -> PLL Clock is Divided by %d (CCLKCFG+1) to produce the CPU Clock\n", clock, clock+1);
	strcat(infoTxt, tampon);
 return 0;
}
// POWER
int PCONPReg(void)
{
	int pconp = LPC_SC->PCONP;
  strcpy(infoTxt, "\n ### PCONP Power Control for Peripherals register 0x400FC0C4 ###\n");
/*	
	( pconp & bit1 ) ? strcat(infoTxt," --- bit1  - PCTIM0 Timer/Counter 0 is ON\n") : strcat(infoTxt," --- bit1 - PCTIM0 Timer/Counter 0 is OFF\n");
  ( pconp & bit2 ) ? strcat(infoTxt," --- bit2  - PCTIM1 Timer/Counter 1 is ON\n") :strcat(infoTxt," --- bit2 - PCTIM1 Timer/Counter 1 is OFF\n");
  ( pconp & bit3 ) ? strcat(infoTxt," --- bit3  - PCUART0 UART0 is ON\n") :strcat(infoTxt," --- bit3 - PCUART0 UART0 is OFF\n");
  ( pconp & bit4 ) ? strcat(infoTxt," --- bit4  - PCUART2 UART2 is ON\n") : strcat(infoTxt," --- bit4 - PCUART2 UART2 is OFF\n");
  // bit5 - Reserved
  ( pconp & bit6 ) ? strcat(infoTxt," --- bit6  - PCPWM1 is ON\n") : strcat(infoTxt," --- bit6 - PCPWM1 is OFF\n");
  ( pconp & bit7 ) ? strcat(infoTxt," --- bit7  - PCI2C0 is ON\n") : strcat(infoTxt," --- bit7 - PCI2C0 is OFF\n");
  ( pconp & bit8 ) ? strcat(infoTxt," --- bit8  - PCSPI is ON\n") : strcat(infoTxt," --- bit8 - PCSPI is OFF\n");
  ( pconp & bit9 ) ? strcat(infoTxt," --- bit9  - PCRTC is ON\n") : strcat(infoTxt," --- bit9 - PCRTC is OFF\n");
  ( pconp & bit10 ) ? strcat(infoTxt," --- bit10 - PCSSP1 is ON\n") : strcat(infoTxt," --- bit10 - PCSSP1 is OFF\n");
  // bit11 - Reserved
  // Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN.
  ( pconp & bit12 ) ? strcat(infoTxt," --- bit12 - PCADC is ON (clear PDN bit in AD0CR before clearing)\n") : strcat(infoTxt," --- bit12 - PCADC is OFF (set this bit before setting PDN in AD0CR)\n");
  ( pconp & bit13 ) ? strcat(infoTxt," --- bit13 - PCCAN1 is ON\n") : strcat(infoTxt," --- bit13 - PCAN1  is OFF\n");
  ( pconp & bit14 ) ? strcat(infoTxt," --- bit14 - PCCAN2 is ON\n") : strcat(infoTxt," --- bit14 - PCAN2 is OFF\n");
*/	
	// PLANTE SUR GPIO avec Keil !
  ( pconp & bit15 ) ? strcat(infoTxt," --- bit15 - PCGPIO/GPIO Interrupts is ON\n") : strcat(infoTxt," --- bit15 - PCGPIO/PCGPIO interrupts is OFF\n");
  ( pconp & bit16 ) ? strcat(infoTxt," --- bit16 - PCRIT Repetitive Interrupt Timer is ON\n") : strcat(infoTxt," --- bit16 - PCRIT Repetitive Interrupt Timer is OFF\n");
  ( pconp & bit17 ) ? strcat(infoTxt," --- bit17 - PCMPCPWM Motor Control is ON\n") : strcat(infoTxt," --- bit17 - PCMPCPWN Motor Control is OFF\n");
  ( pconp & bit18 ) ? strcat(infoTxt," --- bit18 - PCQEI Quadrature Encoder is ON\n") : strcat(infoTxt," --- bit18 - PCQEI Quadrature Encoder is OFF\n");
  ( pconp & bit19 ) ? strcat(infoTxt," --- bit19 - PCI2C1 is ON\n") : strcat(infoTxt," --- bit19 - PCI2C1 is OFF\n");
	
  // bit20 - Reserved
  ( pconp & bit21 ) ? strcat(infoTxt," --- bit21 - PCSSP0 is ON\n") : strcat(infoTxt," --- bit21 - PCSSP0 is OFF\n");
  ( pconp & bit22 ) ? strcat(infoTxt," --- bit22 - PCTIM2 is ON\n") : strcat(infoTxt," --- bit22 - PCTIM2 is OFF\n");
  ( pconp & bit23 ) ? strcat(infoTxt," --- bit23 - PCTIM3 is ON\n") : strcat(infoTxt," --- bit23 - PCTIM3 is OFF\n");
  ( pconp & bit24 ) ? strcat(infoTxt," --- bit24 - PCUART2 is ON\n") : strcat(infoTxt," --- bit24 - PCUART2 is OFF\n");
  ( pconp & bit25 ) ? strcat(infoTxt," --- bit25 - PCUART3 is ON\n") : strcat(infoTxt," --- bit25 - PCUART3 is OFF\n");
  ( pconp & bit26 ) ? strcat(infoTxt," --- bit26 - PCI2C2 is ON\n") : strcat(infoTxt," --- bit26 - PCI2C is OFF\n");
	
 return 0;
}

